Integrated circuit read-only memories (ROMs) may generally be classified into two types: NOR-based ROMs and NAND-based ROMs. In both these types of ROMS, the memory cells are arranged in rows corresponding to wordlines and in columns corresponding to bit lines. A distinction between the two ROM classifications lies in how the columns of memory cells are coupled to their corresponding bit lines. In a NOR-based ROM, each memory cell in a column of memory cells may have a first terminal directly coupled to its corresponding bit line and a second terminal coupled to ground. For example, in an NMOS NOR-based ROM embodiment, each memory cell would comprise an NMOS transistor having its source coupled to ground and its drain coupled to the bit line. In contrast, in a NAND-based ROM, the columns are arranged into memory cells groups such that only one memory cell at the end of each group has a terminal directly coupled to the bit line. A transistor at the remaining end of the group has a terminal coupled to ground. In both types of ROM, the gates of the memory cells are controlled by the corresponding word line.
Given these arrangements, it may be seen that the memory cells in a NOR-based ROM column will all couple in parallel to the corresponding bit line. A NOR-based ROM bit line will be pulled low if any of its memory cells in the corresponding column are turned on because there will then be a path to ground through the conducting memory cell transistor. Thus, the column of memory cells collectively act as a NOR gate with regard to their word lines, thereby leading to the “NOR-based” denotation. Conversely, the memory cells in a NAND-based ROM column group are coupled in series. In such a case, the bit line will be pulled low only if all of the memory cells in the group are conducting. Thus, the memory cells in the group collectively act as a NAND gate with regard to their word lines, thereby leading to the “NAND-based” denotation.
Various techniques have been developed to program these ROMs. For example, the diffusion regions of the memory cell transistors may be programmed to either couple to or not couple to the bit line. Alternatively, the source and drain of a memory cell may be shorted using either via or metal layer programming. Regardless of the type of programming, each ROM type has its advantages and corresponding disadvantages. NAND-based ROMs are denser than NOR-based ROMs but have slower access times. Thus, a ROM designer has been forced to choose between speed and density when selecting between either a NOR-based or NAND-based design. Accordingly, there is a need in the art for ROMs having the density advantages of a NAND-based architecture yet offering the speed advantages of a NOR-based architecture.